A static random access memory (SRAM) device includes more metal oxide semiconductor field effect transistors than a conventional dynamic random access memory (DRAM) device, and can store data without refreshing. However, the cross-coupled nature of SRAM cells may result in manufacturing defects in such memory cells. Such defects may not be detectable when a device is produced, but may manifest themselves after time. Such memory cells are referred to as memory cells having a potential defect property.
Memory cells having a potential defect property can be detected by adjusting a static noise margin. The static noise margin is the margin within which a memory cell sustains its own data when reading data. Memory cells having a potential defect property have a smaller static noise margin than that of normal property memory cells. In other words, the larger static noise margin a memory cells has, the lower the probability that stored data will vary during a read operation.
It is possible to identify memory cells with a potential defect property by lowering the static noise margin of those memory cells. For example, lowering of the static noise margin may be accomplished by lowering an operating voltage applied to memory cells below an operating voltage applied to peripheral circuits (e.g., a row decoder, a column decoder, a bit line precharge and equalize circuit, etc.,). Under such operating conditions, it is possible to quickly identify memory cells with the potential defect property. In accordance with this technique, defective memory cells may be replaced or a chip including such defective memory cells may be discarded.
The above-described technique is disclosed in Japanese Patent Laid-open Nos. 11-185498 and 06-349298, which describe methods where an operating voltage applied to memory cells is lowered while an operating voltage applied to peripheral circuits is maintained.
As is well known to those skilled in the art, a packaged memory device is subject to a burn-in test as an accelerated life test. The burn-in test enables potential defects to be detected and removed in advance by operating memory devices under conditions of increased temperature and operating voltage. During a burn-in test of a packaged device, excessive current is consumed, especially by peripheral devices. In a case where an operating voltage is lowered during the burn-in test, the burn-in test cannot be carried out normally or the burn-in effect may be reduced.